Espressif Systems /ESP32-C6 /SPI0 /SPI_SMEM_DIN_NUM

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Interpret as SPI_SMEM_DIN_NUM

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SPI_SMEM_DIN0_NUM 0SPI_SMEM_DIN1_NUM 0SPI_SMEM_DIN2_NUM 0SPI_SMEM_DIN3_NUM 0SPI_SMEM_DIN4_NUM 0SPI_SMEM_DIN5_NUM 0SPI_SMEM_DIN6_NUM 0SPI_SMEM_DIN7_NUM 0SPI_SMEM_DINS_NUM

Description

MSPI external RAM input timing delay number control register

Fields

SPI_SMEM_DIN0_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN1_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN2_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN3_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN4_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN5_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN6_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DIN7_NUM

the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

SPI_SMEM_DINS_NUM

the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge

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